Cadence Design Systems B2B Case Studies & Customer Successes

A Squared Engineering accelerates marine FEA with Cadence MSC Apex

A Squared Engineering

Advanced Layout Solutions accelerates high-speed PCB design with Cadence Sigrity X

Advanced Layout Solutions (als)

Chris Halford

Lead Engineer, ALS

Airbus Operations GmbH achieves 75% lighter air separator with Cadence generative design

Airbus Operations GmbH

Altair (fabless LTE/IoT chipset maker) achieves up to eight months faster time-to-market and lower development costs with Cadence Design Systems analog IP

Altair (Siemens Xcelerator)

Eran Eshed

Co-Founder and Vice President of Marketing and Business Development

Altair Semiconductor Adopts Cadence Palladium XP Platform for Advanced IoT SoC Development

Altair (Siemens Xcelerator)

Eli Zyss

Vice President of Silicon Design

Amlogic - Customer Case Study

Amlogic

Jerry Cao

Software Engineering Director

Applus+ IDIADA achieves higher-fidelity, faster driving simulation with Cadence Adams Real Time

Applus+ IDIADA

Cadence Launches Xcelium Parallel Simulator, the Industry’s First Production-Proven Parallel Simulator

Arm

Hobson Bullman

General Manager, Technology Services Group

Cadence and Arm Deliver First SoC Verification Solution for Low-Power, High-Performance Arm-Based Servers

Arm

Drew Henry

Senior Vice President and General Manager, Infrastructure Business Unit

Cadence and Arm Deliver First SoC Verification Solution for Low-Power, High-Performance Arm-Based Servers

Arm

Drew Henry

Senior Vice President and General Manager, Infrastructure Business Unit

AUDI Hungaria Zrt achieves faster, more efficient simulation workflows with Cadence ANSA model reduction

AUDI Hungaria Zrt

Gergely Markó

CAE Engineer, AUDI Hungaria Zrt.

Blu Wireless achieves faster 5G mmWave modem tapeout with Cadence Tempus Timing Solution

Blu Wireless

Davide Sarta

SVP Engineering

Cadence Introduces Indago Debug Platform, Improving Debugging Productivity by up to 50 Percent

Bosch

Robert Richter

Senior Expert, ASIC Development

Cavium achieves 4X faster timing closure on high-speed interfaces with Cadence Design Systems' Allegro TimingVision

Cavium

Bill Munroe

Principal PCB Designer

Cavium Deploys the Cadence Palladium Z1 Enterprise Emulation Platform

Cavium

Viral Pandya

Senior Director, Engineering

Cadence and Arm Deliver First SoC Verification Solution for Low-Power, High-Performance Arm-Based Servers

Cavium

Gopal Hegde

VP/GM Data Center Processor Group

Cavium achieves 4X faster timing closure with Cadence Allegro TimingVision

Cavium

Bill Munroe

Principal PCB Designer

Celestial AI achieves 5X faster design closure with Cadence Quantus Insight Solution

Celestial AI

RIAD KACED

PRINCIPAL CAD ENGINEER

Continental Automotive improves occupant safety evaluation with Cadence OIC and META automation

Continental Automotive

Tobias Daecher

CAE Engineer, Continental Automotive

DMP Inc - Customer Case Study

DMP Inc

Eisaku Ohbuchi

Director and General Manager of Core Technology Development

Embraer achieves 3X faster aircraft tooling design with Cadence MSC Apex

Embraer

Ethertronics - Customer Case Study

Ethertronics

Claudio Anzil

VP of Semiconductor Operations

Faraday Technology - Customer Case Study

Faraday Technology

Kun-Cheng Wu

Associate Vice President, SoC Development and Service

Faraday Technology achieves 50x faster ECO implementation and 3x fewer ECO iterations with Cadence Design Systems' Encounter Conformal ECO Designer

Faraday Technology

Huanyu Chen

Senior CAD Engineer

Ford Motor Company reduces physical prototyping with Cadence Adams Real Time

Ford Motor Company

a Fortune 500 financial institution saves $1.7 million with Cadence Reality DC Insight

Fortune 500 Financial Institution

Freescale Semiconductor achieves 2X mixed-signal verification productivity and better bug coverage with Cadence Design Systems' Virtuoso/Incisive platform

Freescale Semiconductor

Arthur Freitas

Design Verification Manager

Fuji Electric - Customer Case Study

Fuji Electric

Naoto Fujishima

General Manager, Device Development Department, Electronic Device Laboratory

Fuji Electric achieves 25% faster design lead time and 26x verification performance with Cadence Design Systems' Virtuoso Accelerated Parallel Simulator

Fuji Electric

Naoto Fujishima

General Manager, Device Development Department, Electronic Device Laboratory

Fujitsu achieves 88% leakage reduction, 36% lower overall power and 50% faster turnaround with Cadence Design Systems' CPF-enabled Low-Power Solution

Fujitsu

Takahide Yoshikawa

Senior Researcher

Fujitsu - Customer Case Study

Fujitsu

Nobuhiko Aneha

Deputy General Manager, Mobile Solution Divisio

Fujitsu Adopts Cadence Palladium Z1 Enterprise Emulation Platform for Post-K Supercomputer Development

Fujitsu

Akira Kabemoto

Corporate Executive Officer and Senior Executive Vice President, Head of Service Platform Business

GKN Aerospace achieves smoother additive manufacturing workflows with Cadence Simufact Additive CAD Export

GKN Aerospace

New Cadence Modus Test Solution Delivers Up to 3X Reduction in SoC Test Time

Global Foundries

Sue Bentlage

Director, ASIC Design and Methodology

Hiroshima University - Customer Case Study

Hiroshima University

Koide

Research Institute for Nanodevice and Bio Systems

Cadence Ushers in New Era of Datacenter-class Emulation with Palladium Z1 Enterprise Emulation Platform

Huawei

Daniel Diao

Deputy General Manager of the Turing Processor Business Unit

Hyundai Motor Company cuts simulation lead time by 95% with Cadence Adams Real Time

Hyundai Motor Company

IBM achieves an 80% reduction in PCB development time with Cadence Design Systems' Allegro System Architect

IBM

Gisbert Thomke

Group Leader

IBM reduces SOI model validation cycle time with Cadence Virtuoso

IBM

Carl Wermer

Advisory Engineer

Cadence Announces Next-Generation JasperGold Formal Verification Platform

Imagination Technologies

Mark Dunn

Executive Vice President

Imagine Communications achieves fewer re-spins and faster, higher-quality high-speed PCB designs with Cadence Design Systems' Allegro and Sigrity

Imagine Communications

Boris Nevelev

Senior Hardware Design Engineer

IN2P3 (CNRS) cuts FPGA board design time by months with Cadence Design Systems' Allegro FPGA System Planner

IN2P3

Daniel Charlet

Design Engineer

IN2P3 accelerates FPGA board design with Cadence Allegro FPGA System Planner

IN2P3

Jean-Pierre Cachemiche

IN2P3 project manager

Cadence Delivers Industry’s First Comprehensive TCL1 Documentation to Support Automotive ISO 26262 Standard

Infineon Technologies

Joerg Schepers

Senior Director, Micronctrollers Powertrain

Inphi Corporation reduces time to market with Cadence Tempus Timing Signoff

Inphi Corporation

Weikai Sun

Vp Engineering

JLG Industries reduces testing time by up to 90% with Cadence Adams Real Time

JLG Industries

L'Occitane - Customer Case Study

L'Occitane

Melexis Technologies NV achieves 15% reduction in IC development time and 200× faster simulation with Cadence Design Systems

Melexis Technologies NV

Gael Close

System Architect

New Cadence Modus Test Solution Delivers Up to 3X Reduction in SoC Test Time

Microsemi

Alan Nakamoto

Vice President Engineering Services

Multigig (fabless semiconductor startup) achieves fast, accurate full‑chip mixed‑signal simulation and first‑time‑right silicon with Cadence Design Systems' Virtuoso simulation and verification suite

Multigig

Haris Basit

Chief Executive Officer

NetSpeed Systems achieves exhaustive, hundreds of times faster cache‑coherent NoC verification with Cadence Design Systems' Palladium XP and Incisive

NetSpeed Systems

JJ Tuan

Chief Verification Architect

Newport Media achieves earlier bug detection and weeks of verification time‑savings with Cadence Design Systems' Incisive Formal Verifier and Assertion‑Based VIP

Newport Media

Sang Tran

Manager VLSI Technology

NIO China improves fatigue analysis efficiency with Cadence Ncode and META tools

NIO China

Nufront achieves 1,000x faster simulation and rapid RTL iteration with Cadence Design Systems' Palladium XP

Nufront

Rock Yang

Vice President of Marketing

NVIDIA achieves a 25% shorter PCB layout design cycle with Cadence Design Systems' Allegro HDI-enabled PCB design flow

Nvidia

Greg Bodi

Senior Manager, System Design Senior Manager, System Design

Cadence Ushers in New Era of Datacenter-class Emulation with Palladium Z1 Enterprise Emulation Platform

Nvidia

Narendra Konda

Director, HW Engineering

Pegatron achieves 67% faster PCB routing and major engineering resource savings with Cadence Design Systems' Allegro PCB Designer (AiDT)

Pegatron

Sky Huang (Yu-Jen Huang)

Deputy Director of Computer-Aided Engineering,

Pegatron boosts PCB routing efficiency with Cadence Allegro PCB Designer

Pegatron

Sky Huang

Deputy Director of Computer-Aided Engineering, Pegatron

Polycom achieves faster PCB design cycles and improved quality with Cadence Design Systems' Allegro PCB Router

Polycom

Greg Rousch

Engineering Manager

QLogic achieves 50% faster ASIC verification and earlier system-level validation with Cadence Design Systems' Palladium XP

QLogic

Greg Kleese

Vice President, Network Solutions Group

Cadence and Arm Deliver First SoC Verification Solution for Low-Power, High-Performance Arm-Based Servers

Qualcomm

Ram Peddibhotla

VP of Product Management

RadiciGroup achieves more reliable recycled polymer design with Cadence Digimat UQ

RadiciGroup

Realtek achieves faster, large-capacity mixed-signal verification and first-time silicon success with Cadence Design Systems' Virtuoso Multi-Mode Simulation

Realtek

Shu-Yi Kao

Manager, Design Technology Department

Realtek Accelerates System-on-Chip Verification with Cadence Palladium XP Platform

Realtek

Yee-Wei Huang

Vice President and Spokesman

Renesas achieves 6X verification productivity with Cadence Verisium and Xcelium ML

Renesas

Tatsuya Kamei

Distinguished Engineer, HPC Digital SOC Division, Renesas Electronics

Renesas accelerates MCU performance verification with Cadence Interconnect Workbench and Palladium Z1

Renesas

Toshinori Inoshita

senior manager, Shared R&D Division 2, Broad-based Solution Business Unit, Renesas Electronics Corporation

Renesas Electronics achieves 250× faster verification and cuts performance analysis from 22 to 9 days with Cadence Design Systems

Renesas Electronics

Toshinori Inoshita

Senior Manager

Ricoh achieves faster ASIC verification — saves 2.5 months and reduces missing test cases by ~22% with Cadence Design Systems' Incisive vManager

Ricoh

Hiroyuki Shibaki

ASIC Design and Verification Manager

RivieraWaves slashes debug cycles 30% and accelerates Bluetooth IP delivery with Cadence Design Systems' Incisive verification solutions

RivieraWaves

Benjamin Lauret

Senior Hardware Engineer

Rohde & Schwarz achieves faster, first-time-right high-frequency IC designs with Cadence Design Systems' Spectre Accelerated Parallel Simulator

Rohde & Schwarz

Gerhard Kahmen

Director of Mixed-Signal IC Design Subdivision,

Rohde & Schwarz achieves 35% faster thermal simulation with Cadence Celsius EC Solver

Rohde & Schwarz

Raimund Blankenburg

Rohde & Schwarz

Cadence Functional Safety Verification Solution Adopted for ISO 26262-Compliant Automotive IC Development Flow at ROHM

ROHM

Akira Nakamura

LSI Product Development Headquarters

S&VL accelerates vehicle development with Cadence Adams Real Time

S&VL Inc

Samsung achieves hundreds of times faster SSD validation and 100% productivity boost with Cadence Design Systems (Palladium XP & Accelerated VIP)

Samsung

Byeong Min

Master of Infrastructure Design Center, System LSI Business,

Samsung - Customer Case Study

Samsung

Tony Gladvin George

Verification Engineer

SCALINX achieves successful 22FDX tapeout with Cadence Pegasus signoff solutions

Scalinx

Hussein Fakhoury

President and CEO, Scalinx

Sharp Corporation achieves 2x faster time-to-market and higher-quality CMOS image sensors with Cadence Design Systems (Encounter RTL-to-GDSII flow)

Sharp

Naoya Fujita

General Manager of Product Planning

Siemens Healthcare achieves 30% verification productivity gain and zero escaped bugs with Cadence Design Systems' Incisive toolflow

Siemens Healthcare

Torsten König

Lead Verification Architect

SiFive achieves faster timing closure and better PPA with Cadence Tempus ECO and Signoff

SiFive

Parthasarathy Narasimhan

Sr. Director, Asic Design Engineering

Skycore achieves scalable, secure power conversion design with Cadence OnCloud

Skycore

Thomas Souvignet

VP of Engineering, Skycore

Spansion achieves 50% faster PDK release and 50% lower PDK testing and qualification costs with Cadence Design Systems

Spansion

Dinraj Shetty

Director, CAD and Methodology

Stellantis achieves faster, consistent crash analysis reporting with Cadence META

Stellantis

Raj Rajagopalan

Sr. Manager Virtual Engineering - Global Safety, Stellantis

STMicroelectronics achieves 3–4 months faster development and mask-cost savings with Cadence Design Systems' Encounter Conformal ECO Designer

STMIcroelectronics

Gianluigi Boarin

Design Manager, Automotive Products Group

STMIcroelectronics - Customer Case Study

STMIcroelectronics

Jean-Paul Henriques

Verification Team Leader

STMicroelectronics achieves 2-month debug time savings and faster RTL/IP verification with Cadence Design Systems' Incisive Debug Analyzer

STMIcroelectronics

S. Sayar

Sr. Verification Engineer

Tait Communications achieves streamlined parts-library management and faster, more accurate PCB design with Cadence Design Systems

Tait Communications

Dave Elder

PCB Design Manager

Tata Motors improves door-closing simulation accuracy with Cadence Adams and Marc co-simulation

TATA Motors

Tatra achieves better truck dynamics and regulatory compliance with Cadence CAE solutions

TATRA

Team Bath Racing Electric achieves compliant battery cooling with Cadence Celsius EC Solver

Team Bath Racing Electric (TBRe)

Ben Ireland-Sinclair

TBRe

Tenstorrent accelerates AI chip verification with Cadence ChipStack AI Super Agent

Tenstorrent

Teradyne achieves faster time to market and higher-quality mixed-signal SoCs with Cadence Design Systems' Virtuoso Multi-Mode Simulation

Teradyne

Dominic Wong

Engineering Tools Strategy Manager

Teradyne Standardizes on Cadence Xcelium Parallel Logic Simulator

Teradyne

Andre Hendarman

Director of Mixed Signal ASIC Development

Texas Instruments - Customer Case Study

Texas Instruments

Suravi Bhowmik

Senior Manager, CMOS Backplane

Texas Instruments achieves 300x faster mixed-signal verification with Cadence Design Systems' Digital/Mixed-Signal (DMS) solution

Texas Instruments

Norbert Isaac

Verification Engineer

Texas Instruments - Customer Case Study

Texas Instruments

Ronald Nerlich

Digital Design Engineer

New Cadence Modus Test Solution Delivers Up to 3X Reduction in SoC Test Time

Texas Instruments

Roger Peters

MCU Silicon Development

The LEGO Group achieves faster, more accurate injection molding simulation with ANSA by Cadence

The LEGO Group

Christoph Mau

CAE Manager, The LEGO Group

Toshiba Adopts Cadence Innovus Implementation System for Production Mobile Memory Controller Design

Toshiba

Kazunari Horikawa

Sr. Manager

Toyota Motor Europe achieves 10x faster HVAC noise simulation with Cadence Design Systems

Toyota Motor Europe

Uniquify achieves 25–30% faster design closure and faster time-to-market with Cadence Design Systems' EDA solutions

Uniquify

Sam Kim

Vice President and CTO

University of California, Irvine improves composite bond testing with Cadence MSC Nastran

University of California, Irvine

UPBracing achieves a lightweight electric race car wheel carrier design with Cadence generative design software

UPBracing

UPEK achieves faster time-to-market and improved design quality with Cadence Design Systems' Incisive Formal Verifier

UPEK

Michele Borgatti

IC Design Manager

VIA Telecom achieves 30% faster product development and first-silicon success with Cadence Design Systems' Encounter Conformal Low Power

VIA Telecom

Frank Hsu

ASIC Design Manager

Volkswagen AG creates human body model variants in minutes with Cadence ANSA Pre-Processor scaling

Volkswagen AG

Volvo Cars reduces NVH encapsulation modeling time by 90% with Cadence ANSA Pre-Processor

Volvo Cars Corporation

Volvo Group achieves faster vehicle NVH optimization with Cadence MSC Nastran FEA Solver

Volvo Group

Xilinx achieves 20–30% faster simulations and shorter development cycles with Cadence Design Systems' Incisive Enterprise Simulator and Specman

Xilinx

Meirav Nitzan

Verification Methodologist

Cadence Launches Protium S1 FPGA-Based Prototyping Platform for Early Software Development

Xilinx

Peter Ryser

Senior Director for System Software, Integration and Validation

Cadence Design Systems B2B Case Studies & Customer Successes

Case Studies

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