Cadence Design Systems B2B Case Studies & Customer Successes

Cadence Design Systems enables global electronic design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Cadence use Cadence software, hardware, IP and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers and research facilities around the world to serve the global electronics industry.

Altair (fabless LTE/IoT chipset maker) achieves up to eight months faster time-to-market and lower development costs with Cadence Design Systems analog IP

Altair

Eran Eshed

Co-Founder and Vice President of Marketing and Business Development

Cavium achieves 4X faster timing closure on high-speed interfaces with Cadence Design Systems' Allegro TimingVision

Cavium

Bill Munroe

Principal PCB Designer

Faraday Technology achieves 50x faster ECO implementation and 3x fewer ECO iterations with Cadence Design Systems' Encounter Conformal ECO Designer

Faraday Technology

Huanyu Chen

Senior CAD Engineer

Faraday Technology - Customer Case Study

Faraday Technology

Kun-Cheng Wu

Associate Vice President, SoC Development and Service

Freescale Semiconductor achieves 2X mixed-signal verification productivity and better bug coverage with Cadence Design Systems' Virtuoso/Incisive platform

Freescale Semiconductor

Arthur Freitas

Design Verification Manager

Fuji Electric achieves 25% faster design lead time and 26x verification performance with Cadence Design Systems' Virtuoso Accelerated Parallel Simulator

Fuji Electric

Naoto Fujishima

General Manager, Device Development Department, Electronic Device Laboratory

Fuji Electric - Customer Case Study

Fuji Electric

Naoto Fujishima

General Manager, Device Development Department, Electronic Device Laboratory

Fujitsu achieves 88% leakage reduction, 36% lower overall power and 50% faster turnaround with Cadence Design Systems' CPF-enabled Low-Power Solution

Fujitsu

Takahide Yoshikawa

Senior Researcher

Fujitsu - Customer Case Study

Fujitsu

Nobuhiko Aneha

Deputy General Manager, Mobile Solution Divisio

IBM achieves an 80% reduction in PCB development time with Cadence Design Systems' Allegro System Architect

IBM

Gisbert Thomke

Group Leader

Imagine Communications achieves fewer re-spins and faster, higher-quality high-speed PCB designs with Cadence Design Systems' Allegro and Sigrity

Imagine Communications

Boris Nevelev

Senior Hardware Design Engineer

IN2P3 (CNRS) cuts FPGA board design time by months with Cadence Design Systems' Allegro FPGA System Planner

IN2P3

Daniel Charlet

Design Engineer

Melexis Technologies NV achieves 15% reduction in IC development time and 200× faster simulation with Cadence Design Systems

Melexis Technologies NV

Gael Close

System Architect

Multigig (fabless semiconductor startup) achieves fast, accurate full‑chip mixed‑signal simulation and first‑time‑right silicon with Cadence Design Systems' Virtuoso simulation and verification suite

Multigig

Haris Basit

Chief Executive Officer

NetSpeed Systems achieves exhaustive, hundreds of times faster cache‑coherent NoC verification with Cadence Design Systems' Palladium XP and Incisive

NetSpeed Systems

JJ Tuan

Chief Verification Architect

Newport Media achieves earlier bug detection and weeks of verification time‑savings with Cadence Design Systems' Incisive Formal Verifier and Assertion‑Based VIP

Newport Media

Sang Tran

Manager VLSI Technology

Nufront achieves 1,000x faster simulation and rapid RTL iteration with Cadence Design Systems' Palladium XP

Nufront

Rock Yang

Vice President of Marketing

NVIDIA achieves a 25% shorter PCB layout design cycle with Cadence Design Systems' Allegro HDI-enabled PCB design flow

Nvidia

Greg Bodi

Senior Manager, System Design Senior Manager, System Design

Pegatron achieves 67% faster PCB routing and major engineering resource savings with Cadence Design Systems' Allegro PCB Designer (AiDT)

Pegatron

Sky Huang (Yu-Jen Huang)

Deputy Director of Computer-Aided Engineering,

Polycom achieves faster PCB design cycles and improved quality with Cadence Design Systems' Allegro PCB Router

Polycom

Greg Rousch

Engineering Manager

QLogic achieves 50% faster ASIC verification and earlier system-level validation with Cadence Design Systems' Palladium XP

QLogic

Greg Kleese

Vice President, Network Solutions Group

Realtek achieves faster, large-capacity mixed-signal verification and first-time silicon success with Cadence Design Systems' Virtuoso Multi-Mode Simulation

Realtek

Shu-Yi Kao

Manager, Design Technology Department

Renesas Electronics achieves 250× faster verification and cuts performance analysis from 22 to 9 days with Cadence Design Systems

Renesas Electronics

Toshinori Inoshita

Senior Manager

Ricoh achieves faster ASIC verification — saves 2.5 months and reduces missing test cases by ~22% with Cadence Design Systems' Incisive vManager

Ricoh

Hiroyuki Shibaki

ASIC Design and Verification Manager

RivieraWaves slashes debug cycles 30% and accelerates Bluetooth IP delivery with Cadence Design Systems' Incisive verification solutions

RivieraWaves

Benjamin Lauret

Senior Hardware Engineer

Rohde & Schwarz achieves faster, first-time-right high-frequency IC designs with Cadence Design Systems' Spectre Accelerated Parallel Simulator

Rohde & Schwarz

Gerhard Kahmen

Director of Mixed-Signal IC Design Subdivision,

Samsung achieves hundreds of times faster SSD validation and 100% productivity boost with Cadence Design Systems (Palladium XP & Accelerated VIP)

Samsung

Byeong Min

Master of Infrastructure Design Center, System LSI Business,

Samsung - Customer Case Study

Samsung

Tony Gladvin George

Verification Engineer

Sharp Corporation achieves 2x faster time-to-market and higher-quality CMOS image sensors with Cadence Design Systems (Encounter RTL-to-GDSII flow)

Sharp

Naoya Fujita

General Manager of Product Planning

Siemens Healthcare achieves 30% verification productivity gain and zero escaped bugs with Cadence Design Systems' Incisive toolflow

Siemens Healthcare

Torsten König

Lead Verification Architect

Spansion achieves 50% faster PDK release and 50% lower PDK testing and qualification costs with Cadence Design Systems

Spansion

Dinraj Shetty

Director, CAD and Methodology

STMicroelectronics achieves 2-month debug time savings and faster RTL/IP verification with Cadence Design Systems' Incisive Debug Analyzer

STMIcroelectronics

S. Sayar

Sr. Verification Engineer

STMicroelectronics achieves 3–4 months faster development and mask-cost savings with Cadence Design Systems' Encounter Conformal ECO Designer

STMIcroelectronics

Gianluigi Boarin

Design Manager, Automotive Products Group

STMIcroelectronics - Customer Case Study

STMIcroelectronics

Jean-Paul Henriques

Verification Team Leader

Tait Communications achieves streamlined parts-library management and faster, more accurate PCB design with Cadence Design Systems

Tait Communications

Dave Elder

PCB Design Manager

Teradyne achieves faster time to market and higher-quality mixed-signal SoCs with Cadence Design Systems' Virtuoso Multi-Mode Simulation

Teradyne

Dominic Wong

Engineering Tools Strategy Manager

Texas Instruments - Customer Case Study

Texas Instruments

Ronald Nerlich

Digital Design Engineer

Texas Instruments achieves 300x faster mixed-signal verification with Cadence Design Systems' Digital/Mixed-Signal (DMS) solution

Texas Instruments

Norbert Isaac

Verification Engineer

Texas Instruments - Customer Case Study

Texas Instruments

Suravi Bhowmik

Senior Manager, CMOS Backplane

Uniquify achieves 25–30% faster design closure and faster time-to-market with Cadence Design Systems' EDA solutions

Uniquify

Sam Kim

Vice President and CTO

UPEK achieves faster time-to-market and improved design quality with Cadence Design Systems' Incisive Formal Verifier

UPEK

Michele Borgatti

IC Design Manager

VIA Telecom achieves 30% faster product development and first-silicon success with Cadence Design Systems' Encounter Conformal Low Power

VIA Telecom

Frank Hsu

ASIC Design Manager

Xilinx achieves 20–30% faster simulations and shorter development cycles with Cadence Design Systems' Incisive Enterprise Simulator and Specman

Xilinx

Meirav Nitzan

Verification Methodologist

No matching case studies

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