Cadence Design Systems

Altair

Eran Eshed

Co-Founder and Vice President of Marketing and Business Development

Altair

Eli Zyss

Vice President of Silicon Design

Amlogic

Jerry Cao

Software Engineering Director

Arm

Drew Henry

Senior Vice President and General Manager, Infrastructure Business Unit

Arm

Drew Henry

Senior Vice President and General Manager, Infrastructure Business Unit

Arm

Hobson Bullman

General Manager, Technology Services Group

Bosch

Robert Richter

Senior Expert, ASIC Development

Cavium

Gopal Hegde

VP/GM Data Center Processor Group

Cavium

Viral Pandya

Senior Director, Engineering

Cavium

Bill Munroe

Principal PCB Designer

Ethertronics

Claudio Anzil

VP of Semiconductor Operations

Faraday Technology

Kun-Cheng Wu

Associate Vice President, SoC Development and Service

Faraday Technology

Huanyu Chen

Senior CAD Engineer

Freescale Semiconductor

Arthur Freitas

Design Verification Manager

Fuji Electric

Naoto Fujishima

General Manager, Device Development Department, Electronic Device Laboratory

Fuji Electric

Naoto Fujishima

General Manager, Device Development Department, Electronic Device Laboratory

Fujitsu

Akira Kabemoto

Corporate Executive Officer and Senior Executive Vice President, Head of Service Platform Business

Fujitsu

Nobuhiko Aneha

Deputy General Manager, Mobile Solution Divisio

Fujitsu

Takahide Yoshikawa

Senior Researcher

Global Foundries

Sue Bentlage

Director, ASIC Design and Methodology

Hiroshima University

Koide

Research Institute for Nanodevice and Bio Systems

Huawei

Daniel Diao

Deputy General Manager of the Turing Processor Business Unit

IBM

Gisbert Thomke

Group Leader

Imagination Technologies

Mark Dunn

Executive Vice President

Imagine Communications

Boris Nevelev

Senior Hardware Design Engineer

IN2P3

Daniel Charlet

Design Engineer

Infineon Technologies

Joerg Schepers

Senior Director, Micronctrollers Powertrain

L'Occitane

Melexis Technologies NV

Gael Close

System Architect

Microsemi

Alan Nakamoto

Vice President Engineering Services

Multigig

Haris Basit

Chief Executive Officer

NetSpeed Systems

JJ Tuan

Chief Verification Architect

Newport Media

Sang Tran

Manager VLSI Technology

Nufront

Rock Yang

Vice President of Marketing

Nvidia

Greg Bodi

Senior Manager, System Design Senior Manager, System Design

Nvidia

Narendra Konda

Director, HW Engineering

Pegatron

Sky Huang (Yu-Jen Huang)

Deputy Director of Computer-Aided Engineering,

Polycom

Greg Rousch

Engineering Manager

QLogic

Greg Kleese

Vice President, Network Solutions Group

Qualcomm

Ram Peddibhotla

VP of Product Management

Realtek

Shu-Yi Kao

Manager, Design Technology Department

Realtek

Yee-Wei Huang

Vice President and Spokesman

Renesas Electronics

Toshinori Inoshita

Senior Manager

Ricoh

Hiroyuki Shibaki

ASIC Design and Verification Manager

RivieraWaves

Benjamin Lauret

Senior Hardware Engineer

Rohde & Schwarz

Gerhard Kahmen

Director of Mixed-Signal IC Design Subdivision,

ROHM

Akira Nakamura

LSI Product Development Headquarters

Samsung

Tony Gladvin George

Verification Engineer

Samsung

Byeong Min

Master of Infrastructure Design Center, System LSI Business,

Sharp

Naoya Fujita

General Manager of Product Planning

Siemens Healthcare

Torsten König

Lead Verification Architect

Spansion

Dinraj Shetty

Director, CAD and Methodology

STMIcroelectronics

S. Sayar

Sr. Verification Engineer

STMIcroelectronics

Gianluigi Boarin

Design Manager, Automotive Products Group

STMIcroelectronics

Jean-Paul Henriques

Verification Team Leader

Tait Communications

Dave Elder

PCB Design Manager

Teradyne

Andre Hendarman

Director of Mixed Signal ASIC Development

Teradyne

Dominic Wong

Engineering Tools Strategy Manager

Texas Instruments

Suravi Bhowmik

Senior Manager, CMOS Backplane

Texas Instruments

Norbert Isaac

Verification Engineer

Texas Instruments

Ronald Nerlich

Digital Design Engineer

Texas Instruments

Roger Peters

MCU Silicon Development

Toshiba

Kazunari Horikawa

Sr. Manager

Uniquify

Sam Kim

Vice President and CTO

UPEK

Michele Borgatti

IC Design Manager

VIA Telecom

Frank Hsu

ASIC Design Manager

Xilinx

Peter Ryser

Senior Director for System Software, Integration and Validation

Xilinx

Meirav Nitzan

Verification Methodologist