Case Study: IN2P3 (CNRS) cuts FPGA board design time by months with Cadence Design Systems' Allegro FPGA System Planner

IN2P3 - Customer Case Study

The National Institute of Nuclear and Particle Physics (IN2P3, CNRS) designs FPGA-based readout and supervision boards for LHC experiments that must process huge data rates and meet aggressive schedules. Engineers faced time‑consuming manual RTL, pin‑placement and routing tasks for large, high‑pin‑count FPGAs (up to ~1,920 pins) and needed a faster, lower‑risk way to select packages and validate layouts before committing to full board designs.

IN2P3 adopted Cadence Allegro FPGA System Planner together with Allegro Design Authoring, PCB Designer and PCB SI to automate pin assignment and enable FPGA–PCB co‑design. The change saved one to two months on initial FPGA design effort (plus ~1 month from co‑design), let teams make late changes in hours instead of weeks, reduced design iterations and costs, and improved routing, layer count and scalability across FPGA sizes.

IN2P3

Daniel Charlet

Design Engineer