Case Study: STMicroelectronics achieves 2-month debug time savings and faster RTL/IP verification with Cadence Design Systems' Incisive Debug Analyzer

STMIcroelectronics - Customer Case Study

STMicroelectronics’ STxP70 team, which develops configurable processors and peripherals, faced a difficult debug challenge for a Verilog RTL data‑cache IP with a complex, third‑party e‑language testbench they did not control. Countless test failures and a slow, print‑based debugging approach made it hard to learn the testbench structure, locate root causes, and progress on schedule.

The team adopted Cadence Incisive Debug Analyzer (alongside Incisive Specman Elite and Incisive Enterprise Simulator), using features like Playback, Smart Log, search, and variable inspection to interactively step forward and backward through simulations and explore the testbench. This approach let them quickly learn the environment, find and fix functional defects, save about two months in the debug cycle, increase confidence for SoC integration, and plan to extend the tool to other IP flows.

STMIcroelectronics

S. Sayar

Sr. Verification Engineer