Case Study: VIA Telecom achieves 30% faster product development and first-silicon success with Cadence Design Systems' Encounter Conformal Low Power

VIA Telecom - Customer Case Study

VIA Telecom, a fabless semiconductor company that designs low-power CDMA baseband processors for mobile handsets, faced growing OEM demands for longer battery life and faster time-to-market. Their manual power-intent verification process was slow and error-prone, putting schedules and product quality at risk as design cycles shortened.

VIA implemented Cadence Encounter Conformal Low Power—together with Encounter RTL Compiler, Encounter Digital Implementation System, and Incisive Enterprise Simulator—to automate power-intent creation and full-chip verification from RTL to GDSII. The new flow was integrated smoothly with local Cadence support, delivering 100% targeted coverage, cutting development time by 30%, enabling 25% more projects with the same resources, and reducing the risk of costly respins.

VIA Telecom

Frank Hsu

ASIC Design Manager