Case Study: Fuji Electric achieves 25% faster design lead time and 26x verification performance with Cadence Design Systems' Virtuoso Accelerated Parallel Simulator

Fuji Electric - Customer Case Study

Fuji Electric, a global supplier of high-performance power devices and modules for new energy, data centers, and automotive markets, needed to develop a new low-power, low-noise driver IC for its power-management systems. The project faced aggressive time-to-market targets and complex, expanding verification requirements to ensure protection functions and high reliability while minimizing external components and cost.

The team adopted Verilog-A modeling and Cadence Virtuoso Accelerated Parallel Simulator (part of Virtuoso Multi-Mode Simulation) integrated with the Virtuoso Analog Design Environment to get SPICE-accurate, scalable simulations. This approach cut design lead time by about 25%, improved verification throughput ~26x, doubled simulation performance, and enabled Fuji Electric to ship a higher-quality product to market sooner.

Fuji Electric

Naoto Fujishima

General Manager, Device Development Department, Electronic Device Laboratory