Case Study: IBM achieves an 80% reduction in PCB development time with Cadence Design Systems' Allegro System Architect

IBM - Customer Case Study

IBM R&D Lab Germany designs extremely large, high-density mainframe PCBs with tens of thousands of interconnects, thousands of pins per component and many wide buses. Traditional schematic workflows were cumbersome—engineers relied on spreadsheet-style signal entry that then had to be converted to HDL, analog elements required manual configuration, and daily compilation cycles could take 8–10 hours—slowing iterations and risking costly delays.

IBM adopted Cadence Allegro System Architect GXL, an integrated front-to-back environment that supports tabular and schematic data, enabling spreadsheet-style signal entry, fast analytics and seamless integration to physical design. The result: tabular input reduces entry time dramatically, compilations that once took hours now complete in seconds, overall PCB development time fell by about 80%, and other IBM divisions are adopting the platform.

IBM

Gisbert Thomke

Group Leader