Case Study: Freescale Semiconductor achieves 2X mixed-signal verification productivity and better bug coverage with Cadence Design Systems' Virtuoso/Incisive platform

Moving to UVM-MS to Meet Coverage Goals

Freescale Semiconductor, a leader in embedded processing for automotive, consumer, industrial and networking markets, faced growing verification complexity as digital logic proliferated in its analog and sensor SoCs. Analog engineers were comfortable with schematic-based, waveform-driven testbenches but had limited expertise in modern, object‑oriented verification languages, making it impractical to maintain separate analog and digital top‑level verification environments. The company needed a more efficient, unified approach to tap both analog and digital expertise and meet coverage goals.

Freescale built a digital‑centric mixed‑signal flow using a domain‑specific layer of preprocessor macros and SystemVerilog APIs, a single hierarchical netlist, and UVM integration, all on the Cadence Virtuoso/Incisive platform (Virtuoso AMS Designer, SimVision, Incisive vManager). By using wreal/real‑number models to speed simulations and forwarding UVM transactions to legacy module APIs, the team achieved orders‑of‑magnitude faster top‑level runs, roughly 2× productivity gains, better coverage and traceability, improved hard‑to‑find bug detection, and easier reuse of block‑level tests and register‑level verification at the IC top level.

Freescale Semiconductor

Arthur Freitas

Design Verification Manager