Case Study: Faraday Technology achieves 50x faster ECO implementation and 3x fewer ECO iterations with Cadence Design Systems' Encounter Conformal ECO Designer

Faraday Technology - Customer Case Study

Faraday Technology Corporation, a leading fabless ASIC and silicon‑IP provider, designs highly customized SoCs and IP for customers demanding fast time‑to‑market and low cost. As SoC projects grew in complexity, Faraday’s manual ECO (engineering change order) flow—editing netlists after synthesis and reconciling logical and physical changes—became slow, error‑prone, and risky, making it difficult to track spare cells, map changes to the physical design, and meet schedule and mask‑cost constraints.

To address this, Faraday implemented Cadence Encounter Conformal ECO Designer to automate functional ECO analysis, optimization, and implementation for pre‑ and post‑mask flows. The tool uses formal equivalence checking and cone‑based analysis to minimize changes and map edits to available gates, avoiding base‑layer mask edits. Since adoption the team has used it on 30+ tapeouts, cut ECO iterations by 3× and ECO implementation time by ~50× (from about 3 days to ~1 hour), enabling earlier netlist handoff, lower manufacturing costs, and faster time to market.

Faraday Technology

Huanyu Chen

Senior CAD Engineer