Case Study: Fujitsu achieves 88% leakage reduction, 36% lower overall power and 50% faster turnaround with Cadence Design Systems' CPF-enabled Low-Power Solution

Faster Hardware Verification and Software Validation for Supercomputers

Fujitsu Microelectronics developed the industry’s first 65nm SoC for mobile WiMAX to meet rapidly rising mobile bandwidth demands, but faced a critical challenge: dramatically reducing overall power and shutoff leakage while moving to smaller geometries. Prior siloed decisions across the design flow hindered consistent low-power results, so Fujitsu needed a way to align power intent and verification from the start to cut chip size, power requirements, and time to market.

Fujitsu implemented a CPF-enabled Cadence Low-Power methodology—integrated into its reference design flow and using Cadence Encounter Digital Implementation, Incisive Design Team Simulator, and Conformal Low Power—to unify design, verification, and implementation. The approach cut leakage by 88%, reduced total power by 36%, halved physical design turnaround time, and improved silicon quality, delivering faster development and a proven platform for future low-power SoC designs.

Fujitsu

Takahide Yoshikawa

Senior Researcher