Case Study: IBM reduces SOI model validation cycle time with Cadence Virtuoso

IBM reduces SOI model validation cycle time by up to 30% with Cadence

IBM, a major technology firm, faced significant challenges in validating advanced semiconductor models for its silicon on insulator (SOI) process nodes. Designing with sub-micron technologies required meeting stringent specifications amid increasing complexity, and the company needed to ensure first-pass success by achieving high correlation between SPICE models and actual silicon. To streamline this critical model qualification process, IBM collaborated with vendor Cadence Design Systems.

Cadence implemented a solution using its Virtuoso Spectre Circuit Simulator and Virtuoso Multi-Mode Simulation to create a robust, unified model qualification flow. This partnership resulted in a 30% reduction in IBM's overall SOI model validation cycle time, improved process node accuracy, and enhanced team productivity. The Cadence team provided invaluable support, aligning regression tests with IBM's procedures to ensure consistent and efficient model verification.

IBM