Case Study: Inphi Corporation reduces time to market with Cadence Tempus Timing Signoff

Inphi cuts signoff runtime by more than 50% with Cadence

Inphi Corporation, a leader in high-speed data movement interconnects, faced a significant challenge taping out their large 7nm designs. They needed to perform full chip flat timing signoff, but their existing static timing analysis (STA) tools consumed nearly all available memory on their 500GB machines to run a single corner, making it impossible to run concurrent modes and corners efficiently. This was a major obstacle to meeting their aggressive time-to-market demands.

Cadence Design Systems implemented its Tempus Timing Signoff solution to address these challenges. The use of Tempus's distributed STA (DSTA) and concurrent multi-mode multi-corner (CMMMC) capabilities allowed Inphi to run flat signoff and flatten all corners in a reasonable time. This solution resulted in a runtime of less than 50% compared to single-corner STA, with CMMMC reporting completed in approximately 10 hours versus over 20 hours previously. Cadence's solution provided better correlation, faster design closure, and an additional 5% power reduction, enabling Inphi to confidently meet their tapeout schedule.

Inphi Corporation