Case Study: Viettel High Tech accelerates 5G chip design and rollout with Synopsys ASIP Designer

Viettel Accelerates 5G Chip Design and Rollout

Viettel High Tech, the R&D arm of Viettel, needed to speed up development of its 5G chip designs while the standard was still evolving and performance demands were rising. The team turned to Synopsys and its ASIP Designer solution to help accelerate its first 5G digital front-end SoC and keep designs adaptable for changing algorithms and power, size, and architecture requirements.

Using Synopsys ASIP Designer, Viettel High Tech streamlined hardware-software co-development, added compiler-in-the-loop and synthesis-in-the-loop flows, and improved verification efficiency. The result was a faster design process that saved months across iterations, delivered more flexible 5G signal processing optimization, and improved performance for Viettel High Tech’s 5G SoC development.

Viettel High Tech

Le-Thai Ha

Principal Engineer