Case Study: Verayo achieves first-pass silicon success for RFID security IC with Synopsys DesignWare AEON NVM IP

Verayo Achieves First-Pass Silicon Success for RFID Security IC with DesignWare AEON NVM IP

Verayo designs security and authentication ICs using Silicon Physical Unclonable Function (PUF) technology and needed non-volatile memory (NVM) for its Vera M1 RFID mixed-signal chip. The team faced tight power, area and cost constraints for a 180‑nm process, required silicon-proven IP that could be ported without reworking their existing design, and had an aggressive time-to-market schedule.

Synopsys’ DesignWare AEON MTP NVM IP met Verayo’s power, area, endurance and process requirements and was ported to the target node with full documentation, training and technical support. With minimal integration effort and collaboration with a third‑party integrator, Verayo achieved first-pass silicon success, met its schedule and hit its performance and cost targets.

Verayo

Richard Sowell

Director of Engineering