Case Study: Test Evolution Corporation achieves faster verification closure and accelerated time-to-market with Synopsys VCS and Verdi

Test Evolution Corporation - Customer Case Study

Test Evolution Corporation (TEV) designs post-silicon validation and ATE products, including a MIPI DSI‑2 protocol test instrument built on a Xilinx FPGA. Facing tight time‑to‑market windows, very large FPGA designs, long simulation runtimes, multi‑engineer debug cycles and the need for UVM‑driven coverage closure, TEV needed a way to shorten verification and debug turnaround without sacrificing quality.

TEV adopted Synopsys VCS simulation with Verdi debug, using VCS’s advanced constraint solver to narrow the test space and nearly halve simulation time, and Verdi’s Reverse Debug, What‑If analysis and Adaptive Exclusion to cut iterations and manual effort. The integrated flow unified design and testbench debug, accelerated coverage closure, saved days of work, and gave TEV the confidence and support to meet their delivery schedule.

Test Evolution Corporation

Al Czamara

VP Engineering