Case Study: SeaMicro achieves 15% FPGA area reduction and lower BOM cost with Synopsys Synplify Pro

Synplify Pro Enables First Time Success Reducing Area by 15% for Next Generation Design, Lowering Risk and Bill of Materials Cost

SeaMicro, a maker of high-density, low‑power data center servers, faced a tight engineering challenge for its next‑generation platform: fit increased ASIC functionality into the same Virtex‑5 prototype FPGA used previously (requiring a ≥15% area reduction) to avoid a costly board respin, while also meeting tighter timing to allow a lower‑cost storage FPGA speed grade and reduce bill‑of‑materials and risk.

Using Synplify Pro FPGA synthesis, the team achieved more than a 15% area reduction and met timing goals, enabling the new fabric design to fit the existing prototype chip and the storage function to run on a lower‑cost -1 speed grade device. The result was higher verification coverage with a single FPGA prototype, avoided board redesign, and lower BOM cost and program risk.

SeaMicro

Dhiraj Mallick

VP of Hardware and System Engineering