Case Study: STMicroelectronics achieves higher reliability and months‑faster FPGA prototyping with Synopsys Synphony Model Compiler

Synopsys and STMicroelectronics High-Level Synthesis Flow Achieves Higher Reliability and Productivity for Multi-rate Digital IF TV ASIC

STMicroelectronics’ Home Entertainment & Displays group needed to develop a complex Digital Intermediate Frequency (DIF) demodulator ASIC featuring multi-rate, real-time DSP (mixers, PLLs, many filters and a sampling-rate converter) plus mixed-signal AGC controls. The team faced tight schedule pressure to explore architecture tradeoffs, deliver an at‑speed FPGA prototype early for algorithm validation, and generate distinct, reliable RTL for both FPGA and ASIC targets.

Using Synphony Model Compiler with Synplify Premier in a Simulink-based high‑level synthesis flow, ST built technology‑independent, multi‑rate models, automatically generated RTL and testbenches, and rapidly iterated designs. The flow produced a full‑speed FPGA prototype months sooner (operating at 160 MHz), delivered high‑quality RTL for a 65 nm ASIC (27,000 registers, 0.89 mm2), reduced schedule risk, and enabled quick product integration.

STMicroelectronics

François Rémond

CAD & Design Methodology Director