Case Study: Open-Silicon achieves three-month schedule savings and first-pass silicon success with Synopsys DesignWare IP

Synopsys and Open-Silicon High Quality IP Saves Three Months on Schedule

Open-Silicon, a full-service ASIC supplier for consumer electronics, needed to deliver a 90 nm networking chip under tight time-to-market, cost and engineering-effort constraints. They required production-proven, interoperable IP for PCI Express and USB that could be integrated quickly and reliably into the customer's end product.

Open-Silicon chose Synopsys DesignWare IP (Hi-Speed USB 2.0 OTG, PCIe controller & PHY, and I/O libraries), which offered up to 15% lower area and power and comprehensive documentation that enabled engineers to configure, integrate and simulate the IP in days. The result was first-pass silicon success, improved area/power performance and ease of integration, and a schedule reduction of nearly three months.

Open-Silicon

Hans Bouwmeester

Director of IP