Case Study: JAXA achieves 3-4x faster modem algorithm design flow with Synopsys SPW

Synopsys and JAXA SPW Enables 3-4x Faster Algorithm Design Flow for Modem Design

The Institute of Space and Astronautical Science (ISAS) at JAXA — a small R&D team collaborating with universities — needed to design a fast (~250M symbols/sec), low‑power modem for nanosatellite downlinks. Their challenges included rapidly developing DSP algorithms and FPGA implementations, supporting modern schemes like OFDM and MIMO, integrating existing C/C++ code, avoiding interface rework between designers, and running many fast simulations to optimize across scenarios.

They adopted Synopsys’ SPW algorithm design environment with extensive, parameterizable model libraries and a model wizard for C/C++ integration, plus built‑in version control, cluster simulation and MATLAB linkage. This model‑based flow cut development effort and time substantially (about 3–4× faster), produced high‑quality, realistic system models, and streamlined conversion from floating‑point algorithms to fixed‑point FPGA implementations for future satellite projects.

JAXA

Naohiko Iwakiri

Institute of Space and Astronautical Science