Case Study: Stellamar achieves first-pass success and faster time-to-market for all-digital ADCs with Synopsys SPW

Stellamar - Customer Case Study

Stellamar is an engineering leader that developed an innovative all-digital ADC technology to implement analog functions in fully digital silicon (FPGA/ASIC). Their main challenges were achieving fast time-to-market, ensuring functional correctness on the first pass with no respins, and using a common testbench for both algorithmic and gate‑level timing simulations.

Stellamar used Synopsys SPW’s model-based algorithm design tool and SPW HDS to model, simulate, verify a bit‑true reference, and generate synthesizable RTL. By reusing a single SPW testbench across algorithm, bit‑true modeling, and RTL verification, they produced power- and area‑optimized ADCs that were proven reliable on prototype/demo boards (including ancillary S/PDIF hardware), enabling first‑time silicon success, reduced cycle time and cost, and easy FPGA/ASIC implementation.

Stellamar

Allan Chin

Chief Executive Officer