Case Study: PLSense achieves 0.45V sub-threshold operation and 5–10× battery-life extension with Synopsys' ARC Data Fusion IP Subsystem

PLSense Achieves 0.45V Operation With Sub-Threshold Technology Implemented on Synopsys’ ARC Data Fusion IP Subsystem

PLSense developed the PLS10, an integrated ultra‑low‑power MCU for battery‑operated IoT that uses near/sub‑threshold technology and Adaptive Dynamic Voltage Control to reduce energy per operation (3–7×) and extend battery life (5–10×). The company’s challenge was to deliver a reliable sub‑threshold SoC and build new low‑voltage libraries and components because many existing IP blocks cannot operate at voltages below threshold.

PLSense implemented Synopsys’ DesignWare ARC Data Fusion IP Subsystem with the ARC EM5D processor and the ARC MetaWare toolkit, enabling fast integration and silicon‑proven support for sub‑threshold operation. The result was first‑pass silicon success with operation down to 0.45 V, meeting performance targets (up to 100 MHz), reducing development time, and delivering the intended ultra‑low‑power MCU.

PLSense

Uzi Zangi

Chief Executive Officer