Case Study: IMEC achieves timing closure and 52.6 MHz for C-programmable ADRES multimedia processor with Synopsys Synplify Premier

IMEC Surpasses Critical Performance Goal for C-Programmable Multimedia ADRES Processor with Synplify

IMEC, a leading nanoelectronics research institute in Leuven, developed ADRES, a C‑programmable reconfigurable processor architecture for handheld multimedia that supports MPEG‑2/4 and H.264 and offers large power-efficiency gains. To validate ADRES for portable devices, IMEC prototyped a multimedia instance on Xilinx Virtex‑4 FPGAs and faced a hard timing target: a 50 MHz clock (required for 30 fps H.264 CIF); their existing Synplify Pro flow only reached 46 MHz.

IMEC switched to Synopsys Synplify Premier, whose graph‑based physical synthesis models FPGA routing and placement, and achieved a predicted 51 MHz and an actual 52.6 MHz, closing timing while cutting place‑and‑route time from 17 to 6 hours. The accurate timing correlation and performance gains validated the ADRES prototype for real‑time video decoding and made Synplify Premier the project’s standard tool for leading‑edge FPGAs.

IMEC

Maryse Wouters

Activity Leader of the Integration Team