Case Study: GUC accelerates chip design with Synopsys floorplan automation

GUC Accelerates Chip Design with Floorplan Automation

GUC, a chip design company, needed to accelerate complex ASIC and SoC floorplanning while meeting aggressive schedules and handling thousands of macros. To address this challenge, GUC worked with Synopsys using FreeForm Macro Placement technology to automate and streamline chip floorplan design.

Synopsys helped GUC dramatically reduce design time, cut floorplan iterations, and improve productivity. The results included 14% lower switching power, 19% less wirelength, reduced leakage power, zero glitch violations, and better timing and congestion, enabling stronger PPA outcomes for advanced AI, HPC, automotive, mobile, and IoT designs.

GUC

Louis Lin

Senior Vice President