Case Study: Fuji Xerox achieves 70% gate-count reduction and 70 pages-per-minute MFP performance with Synopsys ASIP Designer

Fuji Xerox Develops Scanned Image Data Processing ASIP for Full-Color Digital Multifunction Device Using Synopsys ASIP Designer

Fuji Xerox, a leading provider of digital multifunction office devices in Japan, needed a power-, performance- and area-efficient way to implement advanced, software-based angularity correction for a new full‑color MFP that had to operate quietly and remain flexible for algorithm changes. Standard options failed to meet their goals: general-purpose processors couldn't hit the performance target and fixed-function RTL accelerators would blow the gate count and cost targets, so they sought an ASIP-based solution to reduce area, cost and the risk of respins.

Using Synopsys' ASIP Designer to create an application‑specific instruction‑set processor, Fuji Xerox rapidly explored and optimized the processor architecture with compiler‑in‑the‑loop and an auto‑generated SDK. The ASIP approach cut gate count by 70% versus fixed accelerators, enabled implementation on an FPGA (eliminating ASIC NRE and royalties), achieved the 70 pages-per-minute target, and was completed in 14 months by a compact team.

Fuji Xerox

Noriaki Tsuchiya

Manager, Controller Development Group