Synopsys
239 Case Studies
A Synopsys Case Study
PLX Technology, a leading supplier of high‑lane-count PCIe switch silicon, was designing a family of high‑performance switches but faced schedule and quality challenges: synthesis results using traditional wire‑load models did not correlate with post‑layout timing, area, and power, forcing time‑consuming RTL changes and iterations that threatened time‑to‑market and stringent performance targets.
PLX adopted Synopsys’ DC Ultra with Topographical Technology to bring post‑layout placement and delay estimation into synthesis. The flow delivered 10–15% better performance on average, predicted results within about 5% of post‑layout, and eliminated many synthesis/layout iterations—cutting roughly three weeks from the implementation schedule—while improving timing, area, and power convergence across all designs.
Syed Ahmed
Engineering Director