Case Study: Teradici achieves faster, more efficient ASIC-to-FPGA prototyping with Synopsys Synplify Premier

ASIC Prototyping Made Fast and Efficient with Synplify Premier

Teradici develops PCoIP display and I/O chipsets (TERA1100/1200) that enable centralized enterprise computing. To validate increasingly complex ASIC designs built across multiple Xilinx Virtex‑5 FPGAs, the Silicon Validation Group needed faster RTL‑to‑prototype turnaround, reliable timing closure, seamless retargeting of native ASIC code and DesignWare cores to FPGA, and better visibility to trace bugs to their root cause.

They adopted Synopsys Synplify Premier with the Identify RTL debugger and DesignWare support. Synplify Premier’s advanced timing optimizations and gated‑clock conversion improved QoR so much the team could disable some backend optimizations, cutting RTL‑to‑bitfile turnaround from 11–13 hours to 7–8 hours, enabling multi‑clock‑domain support in many devices. Identify’s “qualified sampling” gave selective long‑term visibility for faster root‑cause debugging, and the flow allowed seamless retargeting of ASIC code and IP into FPGA prototypes.

Teradici

David Garau

Engineering Manager