Case Study: Yokogawa halves development time and catches nearly all hardware bugs before prototyping with MathWorks Simulink

Yokogawa Electric Develops Key Components for Next-Generation Optical Networks with Simulink and Mentor Graphics ModelSim

Yokogawa Electric needed to develop two key components for next‑generation optical networks — an ultra‑high‑speed optical packet switch and an Optical Media Manager gateway — while designing control logic and hardware in parallel. To meet tight schedules and avoid costly hardware rework, Yokogawa used MathWorks products (MATLAB, Simulink, Stateflow, Fixed‑Point Designer, HDL Verifier) alongside Mentor Graphics ModelSim to support Model‑Based Design, simulation, and FPGA implementation.

MathWorks helped Yokogawa model and simulate the multiplexer/demultiplexer, error‑correction code, and control logic end to end, convert designs to HDL, and verify them with ModelSim and HDL Verifier, enabling thorough testing before prototyping. As a result, development time was cut in half (two engineers completed work in about six weeks versus more than three months), virtually all coding errors were caught before hardware testing, reliable test data was reused across stages, and the first releases shipped on time and on budget.

Yokogawa

Chie Sato

Development Team Manager