Case Study: Siglead cuts FPGA and ASIC development time by 75% with MathWorks (MATLAB, Simulink, HDL Coder)

Siglead Shortens Development Time for FPGA and ASIC Signal Processing Systems for Storage Devices

Siglead, a developer of signal processing systems for storage devices, faced the challenge of speeding development of two core subsystems: an HDD error‑correction system (FPGA) and an SSD AES scrambling ASIC. The company wanted to avoid the slow, error‑prone workflow of writing reference models in C and hand‑coding HDL, so it adopted MathWorks tools—MATLAB, Simulink, HDL Coder, and Fixed‑Point Designer—to bridge algorithm development and hardware implementation.

Using MathWorks products to model, simulate, verify, and automatically generate synthesizable HDL, Siglead produced bit‑true VHDL, deployed and verified designs on FPGA, and submitted the SSD ASIC to the foundry while moving the HDD design into production. MathWorks’ workflow cut development time by about 75% (HDD from ~4 months to 1 month; SSD from ~2 months to 1 week), reduced design‑change turnaround from days to hours (3 days → 3 hours), and significantly increased engineering productivity.

Siglead

Atsushi Esumi

President and CEO