Case Study: Semtech halves prototyping time and accelerates digital receiver FPGA/ASIC development with MathWorks Model‑Based Design

Semtech Speeds Development of Digital Receiver FPGAs and ASICs

Semtech, a semiconductor maker of wireless RF receivers, needed to accelerate development of a digital receiver chain for FSK and MSK demodulation and evaluate many design alternatives without the overhead and risk of hand-writing VHDL. To address this challenge they expanded their use of MathWorks tools for Model‑Based Design — including Simulink, MATLAB, HDL Coder, HDL Verifier and related toolboxes — to move from manual VHDL reimplementation to a single verified model-based workflow.

Using MathWorks, Semtech modeled and simulated the complete receiver in Simulink (with Communications, DSP System and Signal Processing toolboxes), converted to fixed point with Fixed‑Point Designer, generated production VHDL with HDL Coder, and cosimulated/verified with HDL Verifier. The results: prototypes created 50% faster, verification time reduced from weeks to days, and overall time from requirements to tape‑out cut by about 33%, enabling a more optimized, ASIC‑ready design.

Semtech

Frantz Prianon

IC Design Engineer