Case Study: Renesas System Design Company achieves faster, optimized image-processing ASIC IP development with MathWorks Model-Based Design

Renesas Designs and Implements Image Processing IP Core for ASICs with Model-Based Design

Renesas System Design Company, a design-and-application technology subsidiary of Renesas Electronics, needed to develop and verify core image-processing algorithms for automotive displays and digital imaging ASICs while avoiding late-stage failures and bottlenecks from manual floating‑to‑fixed conversions and hand‑written HDL. To address early functional verification, design flexibility, and faster turnarounds, Renesas adopted MathWorks’ Model‑Based Design using MATLAB and Simulink along with Computer Vision System Toolbox, Fixed‑Point Designer, HDL Coder, and HDL Verifier.

Using MathWorks tools, Renesas built floating‑point models, visualized video‑stream behavior, automated fixed‑point conversion with Fixed‑Point Advisor, and generated synthesizable HDL for cosimulation and synthesis; prototypes were validated on a Stratix FPGA and then synthesized for ASIC. The MathWorks workflow let the team explore multiple optimizations, produce HDL with equal or slightly better area/speed than hand‑written code (fewer gates at 120 MHz and 275 MHz), and dramatically reduce skill bottlenecks—enabling one engineer to learn RTL in six months and a three‑person team to deliver a complex FPGA prototype in the same timeframe.

Renesas System Design Company

Mamoru Kamiya

Senior Design Engineer