Case Study: Rambus accelerates DSP ASIC development with MathWorks HDL Coder

Rambus Develops DSP Blocks for ASICs Using High-Level Synthesis with HDL Coder

Rambus, a developer of high-performance communication silicon, needed to speed up DSP block development for a Gen6 PCIe PHY ASIC with limited time and engineering resources. To reduce reliance on slow manual RTL creation and get verification and back-end work started sooner, Rambus turned to MathWorks tools including HDL Coder, Fixed-Point Designer, and SerDes Toolbox.

Using MathWorks HDL Coder, Rambus generated RTL directly from a verified Simulink DSP model, then customized the code for power optimization and low-power modes while keeping the generated RTL as a reference. This approach let verification and physical design begin in parallel, cut the DSP ASIC design cycle from about one year to three months, retained about 80% of the generated code in the final implementation, and helped the team achieve a first-pass successful lab validation of the test chip.

Rambus

Ehud Nir

Director of Digital Engineering