Case Study: Meteorcomm achieves faster cycle-by-cycle RTL verification with MathWorks Simulink Testbench

Meteorcomm Uses Simulink Testbench for Cycle-by-Cycle RTL Verification Using Multiple Cosimulation Blocks

Meteorcomm, a provider of wireless communications and train control solutions for the railway industry, needed to reuse a digital downconverter from a previous SDR design in a new train communication system. The team wanted a more reliable and efficient way to verify its reference model against the hand-written RTL implementation on a Zynq UltraScale+ MPSoC, rather than relying on a slower, error-prone conventional HDL simulation workflow. MathWorks products used included Simulink and HDL Verifier.

Using MathWorks HDL Verifier, Meteorcomm built a reusable Simulink testbench with HDL cosimulation blocks to drive identical stimulus into both the reference model and the RTL, comparing results cycle by cycle with comparison and Logic Analyzer tools. This reduced development time from nine weeks to three weeks, let one FPGA engineer complete three stimulus checks in under an hour, and made setup for additional test runs take only minutes.