Case Study: Harris Corporation achieves over 85% faster functional verification and defect‑free FPGA designs with MathWorks (HDL Verifier and MATLAB)

Harris Accelerates Verification of Signal Processing FPGAs

Harris Corporation faced a time-consuming, manual process for testing complex FPGA-based signal processing designs across multiple Xilinx Virtex-5 FPGAs. To eliminate tedious file exports and HDL testbench development, Harris adopted MathWorks tools—using MATLAB with DSP System Toolbox and HDL Verifier to link their system models directly to the Cadence Incisive simulator.

MathWorks’ HDL Verifier let MATLAB act as the executable test bench for bidirectional cosimulation, automate stimulus generation and analysis, and run parallel tests across a Linux grid. The MathWorks solution reduced functional verification time by more than 85%, enabled Harris Corporation to complete 100% of planned test cases, and produced a defect-free design that eliminated weeks of lab debug.

Harris Corporation

Jason Plew

Senior Engineer