Case Study: Faraday Technology achieves 57% gate-count reduction and 200× faster simulations with MathWorks Model-Based Design

Faraday Accelerates SIP Development and Shrinks NAND Flash Controller ECC Engine Gate Count by 57% with Model-Based Design

Faraday Technology, a silicon IP provider for SoC and ASIC designs, faced slow, hand-coded workflows for complex memory controllers that limited design iterations and forced worst-case, gate-heavy implementations. To accelerate SIP development and enable system-level exploration, Faraday adopted MathWorks’ Model-Based Design toolchain—using MATLAB, Simulink, Stateflow, Simulink Coder, and HDL Coder—to replace manual SystemC/C++/Verilog coding and speed up architecture exploration.

Using MathWorks tools, Faraday modeled controllers in Simulink/Stateflow, generated C and HDL automatically, and ran cycle-accurate simulations that were 200× faster than prior RTL runs. This faster workflow enabled more design iterations, focused fixes that raised throughput by 15% (and improved a new DDR controller by >33%), and informed trade-offs that cut one ECC engine’s gate count by 57%, while delivering projects on schedule and enabling model reuse for future designs.

Faraday Technology

Ken Chen

ESL Methodology Manager