Case Study: SECO USA achieves zero DDR4 board failures and 35% faster design optimization with Keysight PathWave ADS

SECO Reduces DDR4 Board Failures to Zero and Design Optimization Time by 35%

SECO USA, an embedded-systems and IoT design group, was struggling with DDR4-related PCB failures, shrinking timing and voltage margins, and a matrix of over 300 design variations that made signal- and power-integrity compliance slow and error-prone. To avoid costly re-spins and delayed product releases, SECO USA adopted Keysight’s PathWave Advanced Design System (ADS) along with PathWave Memory Designer and SIPro for accurate EM extraction and memory-channel modeling.

Using Keysight’s PathWave ADS suite, SECO USA automated full-layout EM extraction, statistical and transient simulations, and oscilloscope-linked compliance reporting, which simplified setup and sped verification. Keysight’s solution eliminated DDR/SI board failures (100% reduction to zero), cut design optimization time by 35% (about ten days), accelerated design setup up to 5×, and reduced time-to-sign-off to roughly 30 days, improving both product quality and time to market.

SECO USA

Alessandro Pali

PCB Design