Case Study: Cadence Design Systems achieves rapid on‑the‑fly customization and accurate ASIC floor‑planning with Franz Inc.'s Allegro CL

Design Planner Tool Suite for ASIC Floor-Planning Design

Cadence Design Systems, a leading EDA software provider, developed the Design Planner (DP) suite (Top-Down DP, Logic DP, Physical DP) to improve ASIC floor‑planning and estimate interconnect delays early in deep‑submicron designs. Facing frequent customer requests for custom behavior and the need to run moderate-to-complex algorithms on demand, Cadence selected Franz Inc.'s Allegro CL (ANSI Common Lisp) as the development environment to enable dynamic, on‑the‑fly customization.

Using Franz Inc.'s Allegro CL, Cadence drove DP menus and dialogs with Lisp to allow rapid patches, easy extensions, and flexible tool flows; this implementation delivered more accurate size and performance estimates, reduced the number and length of design iterations, and provided earlier, continually refined interconnect‑delay predictions to avoid costly post‑tapeout surprises. Franz Inc.'s Allegro CL thus enabled faster customization turnaround and improved design predictability for Cadence Design Systems.

Cadence Design Systems

Mark Bales

R & D Fellow