Case Study: eASIC achieves up to 5× faster multi-level PCB and package simulations with Dassault Systèmes' CST Studio Suite

eASIC Reduces Multi-Level Package Design Times with CST Studio Suite

eAsic is a fabless semiconductor company that produces Single Mask Adaptable ASIC™ devices. When designing high‑speed chips, eAsic faced the challenge that the package-to‑PCB channel strongly affects performance, yet full-system 3D electromagnetic simulation of both large PCBs and small, intricate packages was computationally intensive, slow, and memory‑hungry. To tackle this, eAsic turned to Dassault Systemes and its CST Studio Suite.

Dassault Systemes implemented a partitioned co‑simulation approach using CST Studio Suite’s System Assembly and Modeling (SAM) to model package and PCB separately and link them via ports. The solution matched full-model results and lab measurements, accurately reproducing TDR and S‑parameters, while reducing compute needs and delivering up to a five‑fold speed‑up in multi‑level PCB/package simulations—significantly shortening eAsic’s design cycle.

eAsic

LianKheng Teoh

Manager for Package Design